Load driving circuits, such as output buffers of an integrated circuit, may be used to drive large capacitive loads. Such output buffers may be relatively large to provide the capacity to drive large capacitive loads. For example, if a large capacity load is electrically coupled to the output, a large pull-down device may be able to pull-down the voltage level at the load faster than a smaller pull-down device.
Moreover, some conventional output buffers may be subject to noise when switching large loads and/or switching a large number of loads simultaneously. The noise can be generated by parasitic inductance of wires electrically coupled to the output. The noise generated by parasitic inductance of wires can combine with noise generated by the capacitance of the load to cause oscillations at the output of the buffer. Consequently, the output speed of the output buffer may be reduced and if the oscillation of the signal exceeds the noise margin of the output buffer circuit, the output buffer may malfunction.
FIG. 1 is a circuit diagram of a conventional output buffer. Referring to FIG. 1, the conventional output buffer includes a pull-up transistor 111, a pull-down transistor 112, and logic devices 113 through 117. The pull-up transistor 111 is electrically coupled to an external bus line via an output OUT. The pull-up transistor 111 pulls the voltage level at the output OUT up in response to a first output signal of the logic gate 114. The pull-down transistor 112 is electrically coupled to the output OUT and pulls the voltage level at the output OUT down in response to a second output signal of the logic gate 117. The pull-down transistor 112 can be large relative to the pull-up transistor 111. Reference designators DB and EN denote output data and an enable signal for the output buffer respectively.
In the case of a multi-bit semiconductor memory device, the problems described above can become more serious due to the simultaneous switching of outputs. Therefore, it may be beneficial to reduce the magnitude of the noise related to the switching speed of the output buffer by reducing the rate of change of the current.
It is known to apply a low voltage level to the gate of an NMOS transistor of the output buffer in an initial stage and apply a power supply voltage after a certain time has passed to reduce the rate of change of the current. Such techniques are discussed, for example, in an article by Miyaji, entitled A 25ns 4Mbit CMOS SRAM with dynamic bit-line loads, IEEE J. Solid-State Circuits, vol. 24, pp. 1213-1217, October 1989.
It is also known to provide an NMOS transistor and a PMOS transistor of the output buffer are comprised of N transistors electrically coupled in parallel and time taken to turn on the respective transistor is controlled. Such techniques are discussed, for example, in an article by Senthinathan entitled Application specific CMOS output driver circuit design technique to reduce simultaneous switching noise, in IEEE J. Solid-State Circuits, Vol. 28, pp. 1383-1388, December 1993. Unfortunately, according to the techniques discussed in Miyaji and Senthinathan, it may not be possible to know the load conditions in advance.
It is also known to control the output current of the output buffer by designating a slow mode and a fast mode from the outside according to the load condition of the output. Control of fast and slow modes is discussed, for example, in an article by Furutani entitled Adjustable output driver with a self-recovering Vpp generator for a 4M.times.16 DRAM, in IEEE J. Solid-State Circuits, Vol. 19, pp. 308-310, March 1994. Unfortunately, according to the techniques discussed in Furutani, additional pins may be needed on the device in order to designate the load condition external to the device.